layout design manager

Synopsys provides silicon design, IP, simulation and analysis solutions, and design services. It partners with customers across a wide range of industries to strengthen their R&D capabilities and productivity and enable innovation in AI-powered products.

• Lead a team of SRAM memory layout engineers through the full development cycle, from initial floorplanning and resource allocation to physical verification signoff and product release
• Own layout execution for memory arrays, bitcells, peripheral circuits, power distribution networks, and complete memory instances, ensuring they meet PPA, reliability, and manufacturability targets
• Resolve complex physical design challenges, including DRC, LVS, ERC, antenna violations, EM/IR analysis, routing congestion, and parasitic extraction issues across advanced FinFET and GAA nodes
• Manage project schedules, resource allocation, technical dependencies, and risk mitigation across concurrent memory compiler and embedded memory development efforts
• Collaborate with circuit design, memory architecture, characterization, CAD tool development, physical verification, process technology, and foundry engineering teams to align layout execution with product requirements
• Build and improve layout methodologies, automation scripts, design reuse frameworks, and standardization practices to increase team efficiency and reduce development cycle time
• Mentor engineers, establish technical best practices, conduct performance reviews, support hiring and onboarding, and grow the technical capability of the layout organization
• Deliver embedded SRAM memories and memory compiler products that meet PPA targets and enable customer tapeouts on schedule
• Reduce layout development cycle time and improve design quality through methodology improvements, automation, and reuse strategies across projects
• Build a high-performing layout team with strong technical depth, clear career growth paths, and the ability to handle increasing complexity at advanced nodes
• Resolve critical physical design issues that unblock product releases and prevent costly respins or yield losses
• Strengthen collaboration between layout, circuit design, and verification teams to reduce miscommunication and rework
• Establish layout best practices and design standards that improve consistency, quality, and knowledge transfer across the memory IP organization
• Enable memory IP customers to achieve their performance, power, area, and time-to-market goals by delivering robust, manufacturable memory solutions

• Bachelor's or master's degree in electrical engineering, Electronics, Microelectronics, or a related field
• 7+ Years of hands-on experience in SRAM memory layout development, including bitcells, arrays, peripheral circuits, and full memory integration
• Deep understanding of SRAM architecture, memory compilers, and how layout decisions affect performance, power, area, yield, and reliability
• Strong working knowledge of DRC, LVS, ERC, antenna checks, EM/IR analysis, parasitic extraction, and advanced-node layout constraints
• Experience leading engineering teams or managing complex technical projects with multiple stakeholders and dependencies
• Будет плюсом: Proficiency with industry-standard custom layout tools and physical verification flows, experience with layout automation and scripting, SRAM memory compiler development across multiple process technologies, advanced FinFET or GAA nodes

• Comprehensive health, wellness, and financial benefits