Digital Design Verification Engineer

Synopsys develops chip design, verification, and IP integration technology, enabling the creation of high-performance silicon chips and software. Its technology supports applications ranging from self-driving cars to learning machines.

• Apply AI techniques and agentic AI tools to accelerate design verification, including generating verification plans, test cases, coverage, and debug collateral
• Implement reference and unified verification flows for Synopsys digital IP products using EDA tools
• Build scalable verification infrastructures for complex IP and SoC projects
• Define, document, and share verification methodologies and standards with global engineering teams
• Lead and mentor junior engineers
• Drive technical initiatives and independently manage high-impact assignments
• Collaborate with tool development teams to influence product evolution and optimize verification workflows
• Troubleshoot, optimize, and refine verification processes and flows for customers and internal stakeholders
• Elevate digital IP verification capabilities through robust, unified, and scalable methodology solutions
• Streamline and standardize verification processes to accelerate time-to-market for high-performance silicon products
• Equip global verification teams with verification flows, tools, and practices
• Shape verification strategy for next-generation IP and SoC offerings
• Mentor and develop verification engineers
• Provide feedback on and contribute to the evolution of the EDA tool ecosystem
• Improve verification methodologies and support Synopsys’ position in the semiconductor industry

• At least 12 years of hands-on experience in IP/SoC verification, with a proven record of technical contributions
• Good understanding of agentic AI technologies, specifically Cursor and/or VS Code Copilot
• Passion for learning agentic AI mechanisms and applying them to design verification
• Familiarity with Synopsys verification tools, including VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs
• Ability to validate verification flows and infrastructure for complex digital designs
• Solid programming and scripting skills in SystemVerilog, UVM, Tcl, Python, or similar languages
• Bachelor’s or Master’s degree in electrical, electronics, or computer engineering
• Experience multitasking and independently managing technical projects
• Ability to document, communicate, and share technical methodologies across global teams
• Innovative problem-solving skills and ability to thrive in dynamic, fast-paced environments
• Excellent communication skills, including explaining complex technical topics to diverse audiences
• Mentoring skills and a collaborative approach to team development
• Strategic thinking, attention to detail, and commitment to quality
• Self-motivation, initiative, adaptability, and resilience
• Будет плюсом: exposure to agentic AI EDA tools

• Comprehensive health, wellness, and financial benefits, including monetary and non-monetary rewards
• Salary range and benefits details will be provided during the hiring process